A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks (PLBs) interconnected by programmable routing resources and programmable I/O cells. Programming of these logic blocks, routing resources and I/O cells is selectively completed to make the necessary interconnections that establish a configuration thereof to provide desired system operation/function for a particular circuit application.
As is well known, it is desirable to complete diagnostic testing of all types of integrated circuits including FPGAs. Toward this end, the present inventors have recently developed two methods of built-in self-testing for FPGAs. These methods are set out in detail in U.S. Pat. No. 5,991,907 and U.S. Pat. No. 6,003,150 referenced above. The full disclosures in these patent applications are incorporated herein by reference.
In each of these methods, the reprogramability of an FPGA is exploited so that the FPGA is configured exclusively with built-in self-test logic during the testing. In this way, testability is achieved without overhead. The built-in self-test logic simply "disappears" when the circuit is reconfigured for its normal operation. The only cost for these testing methods is the additional memory for storing the data required for reconfiguring the FPGA but this may be made a part of the test machine environment e.g. automatic testing equipment (ATE), central processing unit (CPU) or maintenance processor not involving FPGA resources.
While both of these earlier methods provide reliable diagnostic testing, they could be improved upon. The first test method, disclosed in U.S. Pat. No. 6,003,150, utilizes significant amounts of global routing. The second test method, disclosed in U.S. Pat. No. 5,991,907 utilizes an iterative logic array (ILA) architecture where most signals can be routed locally. However, the test time is approximately 33% longer than the first method.